(A) Field of the Invention
The present invention relates to a recessed channel transistor and method for preparing the same, and more particularly, to a recessed channel transistor with elevated doped regions serving as source and drain regions and a method for preparing the same.
(B) Description of the Related Art
FIG. 1 illustrates a planar channel metal-oxide-semiconductor field effect transistor (MOSFET) 10 according to the prior art. The planar channel transistor 10 is an important basic electronic device including a semiconductor substrate 12, a gate oxide layer 14, a conductive metal layer 16 serving as the gate and two doped regions 18 serving as the source/drain in the semiconductor substrate 12. The planar channel transistor 10 may further include a nitride spacer 22 positioned on the sidewall of the conductive metal layer 16 for isolating the conductive metal layer 16 from the other electronic device on the semiconductor substrate 12.
As semiconductor fabrication technology continues to improve, sizes of electronic devices are reduced, and the size and the channel length of the planar channel transistor 10 also decrease correspondingly. The planar channel transistor 10 in FIG. 1 has been widely used in the integrated circuit; however, the continuous decreasing of the size and the channel length of the planar channel transistor 10 results in a serious interaction between the two doped regions 18 and a carrier channel 24 under the gate oxide layer 14 such that the controlling ability of the conductive metal layer 16 on the switching operation of the carrier channel 24 is reduced, i.e., causes the so-called short channel effect, which impedes the functioning of the planar channel transistor 10. To address this problem, researchers developed the so-called recessed channel transistor with a recessed gate sandwiched between the two doped regions and an increased channel length.
FIG. 2 to FIG. 4 illustrate a method for preparing a recessed channel transistor 30 according to the prior art. First, a pad oxide layer 36 is formed to cover a semiconductor substrate 32 with a trench isolation structure 34, and an etching mask 38 having a plurality of openings 40 is then formed on the pad oxide layer 36. Subsequently, a dry etching process is performed to remove a portion of the semiconductor substrate 32 under the openings 40 of the etching mask 38 so as to form a plurality of recesses 42 in the semiconductor substrate 32, as shown in FIG. 3.
Referring to FIG. 4, after removing the etching mask 38, recessed gates 44 filling the recesses 42 and word lines 46 connecting the recessed gates 44 are formed. Subsequently, an implanting process is performed to implant dopants into the semiconductor substrate 32 and form two doped regions 48 serving as the source and the drain at two sides of the recessed gates 44 in the semiconductor substrate 32.
The recessed channel transistor 30 has shown good data retention time characteristics as compared to the planar channel transistor 10 because of its superiorities in drain-induced barrier lowering (DIBL), sub-threshold slope, and junction leakage. However, the recessed channel transistor 30 exhibits a significant gate induced drain leakage (GIDL) current due to the large overlap between the recessed gate 44 and the source/drain regions 48 as compared to the planar channel transistor 10, which exhibits substantially no overlap between the gate 16 and the source/drain regions 18, as shown in FIG. 1.